1. Field of the Invention
The present invention relates to a pipeline A/D converter, and more particularly to a pipeline A/D converter obtained by cascading a plurality of low-bit A/D conversion stages (hereinafter, simply referred to as “stage”), for obtaining a final digital signal based on a digital signal obtained in each stage.
2. Description of the Background Art
Development in system LSI technology in recent years has enabled mounting of a large-scale system on a single LSI. A data converter is indispensable for input/output of an analog signal in such a system LSI. In the system LSI, as various types of information such as a sensor or image signal or a radio signal have more often been input, a plurality of A/D converters are often mounted on a single system LSI. Under such circumstances, pipeline A/D converters have increasingly been used in recent years as circuits excellent in terms of occupied area and power consumption. Meanwhile, further reduction in the area or lower power consumption is required also in pipeline A/D converters excellent in terms of occupied area and power consumption. Here, a shared amplifier configuration has been proposed as measures to meet such demands (see, for example, Japanese Patent Laying-Open No. 2005-252326).
According to the shared amplifier configuration, with attention being paid to the fact that an amplifier in a general pipeline A/D converter operates during only half of one cycle, (1) the amplifier is shared between two adjacent pipeline stages, or (2) two sets of capacitors are provided to perform an interleaved operation so that the amplifier is shared by the two sets of capacitors.
In the case of (1), the amplifier requiring largest area in the pipeline stage is shared by two stages so that the area can significantly be reduced, and efficiency in use of the amplifier is doubled so that power consumption can be lowered. Meanwhile, in the case of (2), though disadvantageous in terms of the area because of provision of two sets of capacitors, an operating time of the amplifier can be doubled so that a settling time required in the amplifier is significantly reduced, power required in the amplifier is significantly lowered, and the area of the amplifier can also be made smaller.
It is likely that the shared amplifier configuration attaining such features will further increasingly be employed in the future, however, no period for resetting the amplifier is available in the pipeline stage adopting the shared amplifier configuration. Accordingly, a large potential difference between differential input terminals of the amplifier, caused by excessive input, is taken over for a plurality of cycles, which results in a great error during the operation over several cycles. Mechanism of this phenomenon is as described below.
The pipeline stage constituting the pipeline A/D converter includes a switched capacitor circuit. With the effect of negative feedback and artificial ground of the amplifier, a sampled analog signal Vin is multiplied by a specific multiplier α (α is typically set to 2 or 4), and a reference voltage Vr=k·Vref (k=0, ±1, . . . ±(α−1); Vref represents a reference voltage determining an input range) selected in accordance with a level of analog signal Vin is subtracted (Vout=kVin−Vr).
If signal Vin at such an excessively high level as exceeding Vref is input in performing this calculation, a voltage represented by Vout=kVin−Vr may not be output, because the output range of the amplifier is restricted by a power supply voltage Vdd. Here, the amplifier cannot make transition to a state of artificial ground, and a large potential difference is created between the differential input terminals of the amplifier.
In order to solve this problem, it is possible to provide a limiter circuit for restricting an input voltage. The limiter circuit is mainly constituted of a comparator and a switch, however, slight deviation in accuracy of the comparator or in a reference potential is doubled or quadrupled per one stage, which results in a value significantly deviating from the input range after several stages. Thus, the possibility of overflow again arises. Accordingly, a large number of limiter circuits are required in order to avoid a great error. Meanwhile, if safety is to be ensured, a limiter circuit is required for each stage and the area therefor is very large. In addition, as a delay path is inserted in a signal path, speed characteristic of a circuit preceding the limiter circuit should be improved and increase in current consumption results.